Depth estimation is one of the key techniques in the front-end of stereoscopic video system which still faces some challenges,such as the depth accuracy,real-time processing and high resolution depth map generation.This paper propos es a hardware solution for real-time depth estimation to mainly resolve the speed issue,the accuracy as well as the high r esolution.The system is implemented on a single FPGA,which uses match algorithm mixed by census transform and sum of absolute d ifferences (SAD) to obtain a dense depth map. The design makes full use of the massive parallel resources and pipeline archite ctures of FPGA to improve data through-out and system clock frequency.Experiment results show that the proposed method is reas onable and can achieve real-time depth estimation for the full high definition (HD) (1920×1 080)resolution video,with the disparity search range up to 240pixels and the fr ame rate up to 69.6frame/s.The performance of the proposed hardware system mee ts the requirements of 3D video system.