基于DPRAP的高级残差预测算法可重构设计与实现
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(1.西安邮电大学 计算机学院,陕西 西安 710121; 2.西安邮电大学 电子工程学院,陕西 西安 710121)

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谢晓燕(1972-),女,硕士,教授,硕士生导师,主要研究领域是多媒体数据处理和并行计算架构设计.

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国家自然科学基金资助项目(61834005,7,61802304,61602377,61874087,61634004)和陕西省重点研发计划 (2021GY029,2021KW-16)资助项目 (1.西安邮电大学 计算机学院,陕西 西安 710121; 2.西安邮电大学 电子工程学院,陕西 西安 710121)


Reconfigurable design and implementation of advanced residual prediction algorit hm based on DPRAP
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(1.School of Computer Science,Xi′an University of Posts and Telecommunications, Xi′an, Shaanxi 710121, China; 2.School of Electronic Engineering, Xi′an Univers ity of Posts and Telecommunications, Xi′an,Shaanxi 710121,China)

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    摘要:

    针对三维高效视频编码(three dimensional-high efficiency video coding,3D- HEVC)中高级残差 预测(advanced residual prediction,ARP)算法没有充分利用深度图的数据特性而导致 编码时间长、硬件加 速资源占用率高的问题,提出了一种基于可重构硬件实现的ARP快速选择算法。本文首先依 据深度图的数据特 性将其分为近中远3个区域,然后设定阈值对不同区域下的高级残差预测算法进行快速选择 ,从而达到减少编 码时间的目的。实验结果表明与标准平台HTM-16.1相比快速选择算 法在平均峰值信噪比(peak signal to noise ratio,PSNR)的损耗仅为0.019 dB的情况下 编码时间降低8.10%。最后利用动态可编程可重构阵列处理 器(dynamic programmable reconfigurable array processor,DPRAP)对ARP快速选择算法 进行并行加速,再 基于阵列处理器的重构机制提出一种可重构实现方案,达到对算法加速的同时降低硬件资源 占用率的目的。实 验表明所设计的可重构方案与并行方案相比总体减少了50%的处理元(process element,PE)数量和33.23%的 指令数,平均加速比达到1.9。优化前后的算法结合视差估计进行对 比验证,平均加速比达到2.5。因此本文 对3D-HEVC算法的实时视频编码具有一定的参考价值。

    Abstract:

    In order to solve problems of long encoding time and high hardware accelerat ion resource occupancy rate caused by the advanced residual prediction (ARP) algorithm which does not make f ull use of the data characteristics of depth map in three-dimensional high efficiency video coding (3D-HEVC),a fast ARP selection algorithm based on reconfigurable hardware implementation is proposed.Firstly,the depth map is di vided into three regions according to its data characteristics,and then the threshold is set to select the advanced resid ual prediction algorithm in different regions quickly,so as to reduce the coding time.The experimental results show that com pared with the standard platform HTM16.1,the fast selection algorithm reduces t he encoding time by 8.10% when the average peak signal to noise ratio (PSNR) loss is only 0.019dB.Finally,the dynamic programmable recon figurable array processor (DPRAP) is used to accelerate the ARP fast selection algorithm in parallel,and then a reconfigurab le implementation scheme is proposed based on the reconfiguration mechanism of the array processor,so as to accelera te the algorithm and reduce the hardware resource occupancy.The experimental results show that compared with the paralle l scheme,the total number of the process element (PE) and instructions are respectively reduced by 50% and 33.23%,and the average speedup is 1.9.The algorithm before and after optimization is compared with disparity estimation,a nd the average speedup is 2.5.Therefore, this study has a certain reference value for real-time video coding of 3D-HEVC algorithm.

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谢晓燕,王淑欣,朱筠,张西红,姬申涛.基于DPRAP的高级残差预测算法可重构设计与实现[J].光电子激光,2022,33(2):217~224

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  • 收稿日期:2021-05-14
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  • 在线发布日期: 2022-03-24
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